The Successful Tape-Out of 800mm2 Large Chip Under the FPU Architecture of Nano Labs

Tuesday, 28. December 2021 21:31

Singapore, Singapore--(Newsfile Corp. - December 28, 2021) - Recently, Nano Labs released a piece of news that the Cuckoo 2 chip has been successfully taped out. This is a high-throughput computing chip based on the FPU architecture with a chip area of 800mm2, which is the largest 3D packaged near-memory computing (NMC) chip.

Computing in the era of big data takes "fast calculation" as the core indicator of high performance computing. The following intelligent era has made high throughput computing with data "being processed in the flow" a new computing model, and made the "data processing efficiency" of multitasking per unit time a key indicator. Nano Labs's PFU architecture is a high-throughput computing chip architecture with independent intellectual property rights proposed for the computing needs of the next-generation Internet, Internet of Things and Metaverse, characterized by multi-core, flexible edge network and high-bandwidth storage (HBM).

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Following the successful mass production of the Cuckoo 1 chip, the Cuckoo 2 chip that has been successfully produced in mass recently has been greatly improved in performance indicators. Cuckoo 2 chip is made of computing and storage through 3D advanced packaging, including a storage chip with 38nm process and a capacity of 6GB and a computing module with 60 computing cores and 40nm process. Because it adopts FPU design architecture, the number of channels of near-memory computing reaches more than 1500, making the theoretical bandwidth of the memory reach 6TB/s, which is 15 times that of M1 Max.

In the third quarter of this year, Apple released the M1 Max chip, which supports 64G of memory, with a maximum memory bandwidth of 400GB/S. Near-memory computing and further processing in memory (PIM) are one of the core technologies of high-throughput computing. In particularly, in calculations such as artificial intelligence training of large models, the multiple high-speed reading and writing of data between the computing core and the memory has become a bottleneck in efficiency and energy consumption, and the unique multi-core and multi-channel design and patented technology in the FPU architecture quickly iterate the high-performance Cuckoo 2 on the basis of the Cuckoo 1, which proves the advancement of the design.

Cuckoo 2 has a large chip area of 800mm2, which is a challenge for packaging. Nano Labs's 3D high-end packaging technology has also made a breakthrough in this mass production, paving the way for the future launch of more powerful near-memory computing large chips based on FPU.

Nano Labs is committed to "future computing needs". In the upcoming Metaverse era, the current computing power infrastructure, chips, server equipment, etc. required by AI, blockchain, 3D space computing and 8K HD are obviously insufficient, and greater and more radical innovations can meet the future needs.

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Media Contact
Jason Lee

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